1. Field of the Invention
The present invention relates to dual loop PLLs (Phase Looked Loop) having a frequency comparison loop and a phase comparison loop, and to multiplication clock generators using the dual loop PLL.
2. Description of Related Art
Conventionally, as the PLL included in multiplication clock generators or the like, there is known a dual loop PLL having a frequency comparison loop and a phase comparison loop, the dual loop PLL for obtaining wideband phase synchronization without increasing the gain of a voltage controlled oscillator. An example thereof is disclosed, for example, in the following Non-Patent Document 1. Yi-Cheng Chang, Edwin W. Greeneich, “MONOLITHIC PHASE-LOCKED LOOP CIRCUITS WITH COARSE-STEERING ACQUISITION AID” Circuits and Systems, 1999. 42nd Midwest Symposium on, Volume: 1, 1999 Page(s): 283-286 vol. 1
The dual loop PLL has the advantage of decreasing the influence, which the variations of an input voltage to a voltage controlled oscillator have on the oscillation frequency, because the gain of the voltage controlled oscillator can be reduced even if the dual loop PLL is wide-banded. Moreover, this dual loop PLL has the function to autonomously correct the characteristics of the voltage controlled oscillator to the required characteristics by the frequency comparison even if the characteristics of the voltage controlled oscillator vary due to variations in the manufacturing process.
FIG. 8 shows an example of a circuit configuration of a conventional dual loop PLL. The dual loop PLL shown in FIG. 8 comprises a phase comparator 1p, a charge pump 2p, an operation mode selector switch 3p that switches between a phase comparison loop (P side) and a frequency comparison loop (F side), a loop filter 4p, a voltage controlled oscillator (VCO) 5p, a frequency divider 6p, a frequency comparator 7p, an up/down counter 8p, a VCO characteristic control circuit 9p, a voltage reference (Vref) 10p, an external reference clock line CLex 11p, an internal clock line CLin 12p, a frequency comparison stop signal line FSTOP 13p, a PLL power-on control line PON 14p, and an output line OUT 15p of the voltage controlled oscillator 5p. 
Hereinafter, the operation of the dual loop PLL is described with reference to FIG. 8.
First, in the state where an enable signal is inputted to the PLL power-on control line PON 14p, the dual loop PLL sets the operation mode selector switch 3p to the F side, and thereby the input voltage to the loop filter 4p is a voltage from the voltage reference Vref 10p and the loop from the phase comparator 1p is open. Thus, the loop is a frequency comparison loop passing through the frequency comparator 7p, up/down counter 8p, VCO characteristic control circuit 9p, voltage controlled oscillator 5p, and frequency divider 6p. 
In the above-described frequency comparison loop, a fixed reference voltage is supplied to the input voltage of the voltage controlled oscillator 5p from the voltage reference Vref 10p, and the voltage controlled oscillator 5p operates only in the frequency comparison mode. In this frequency comparison mode, the frequency comparator 7p compares the frequency of the internal clock line CLin 12p, which is obtained by dividing the output frequency of the voltage controlled oscillator 5p by the frequency divider 6p, with the frequency of the external reference clock line CLex 11p, and outputs an UP signal when the frequency of the external reference clock line CLex 11p is higher than the frequency of the internal clock line CLin 12p, and outputs a DOWN signal when it is lower. Here, the UP signal is a signal to operate as to increase the counter value of the up/down counter 8p, and the DOWN signal is a signal to operate as to decrease the counter value of the up/down counter 8p. 
Upon receipt of the UP signal or DOWN signal from the frequency comparator 7p, the up/down counter 8p will add or subtract “1” to/from the count value in response to this signal. The VCO characteristic control circuit 9p receives a digital output from the up/down counter 8p, and shifts the V-F characteristics (the input voltage-output frequency characteristic) of the voltage controlled oscillator 5p in response to this digital output value, thereby changing the output frequency of the voltage controlled oscillator 5p. Accordingly, the frequency of the internal clock line CLin 12p will increase or decrease to come closer to the frequency of the external reference clock line CLex 11p. 
A series of operations of: carrying out the frequency comparison of the external reference clock line CLex 11p with the internal clock line CLin 12p; changing the count value of the up/down counter 8p in response to the results of the comparison; and changing the V-F characteristics of the voltage controlled oscillator 5p by means of the VCO characteristic control circuit 9p to bring the frequency of the internal clock line CLin 12p closer to the frequency of the external reference clock line CLex 11p, will be repeated until the both frequencies become substantially equal, and a signal is outputted to the frequency comparison stop signal line FSTOP 13p from the frequency comparator 7p. 
When the frequency comparison stop signal is outputted to the frequency comparison stop signal line FSTOP 13p from the frequency comparator 7p, the count value of the up/down counter 8p is fixed. Moreover, the operation mode selector switch 3p switches from the F side to the P side, and the output side of the charge pump 2p is coupled to the input side of the loop filter 4p. Accordingly, the loop switches to the phase comparison loop passing through the phase comparator 1p, charge pump 2p, loop filter 4p, voltage controlled oscillator 5p, and frequency divider 6p. 
In this phase comparison loop, the phase comparator 1p carries out phase comparison of the external reference clock line CLex 11p with the internal clock line CLin 12p, and outputs an UP signal for the time period corresponding to the phase difference when the phase of the external reference clock line CLex 11p leads to the phase of the internal clock line CLin 12p, and outputs a DOWN signal for the time period corresponding to the phase difference when it lags. The charge pump 2p charges and discharges the loop filter 4p in response to the UP signal and DOWN signal from the phase comparator 1p. The loop filter 4p integrates the charge and discharge currents from the charge pump 2p to convert them to a DC voltage, which is employed as an input voltage to the voltage controlled oscillator 5p. This input voltage will change the output frequency of the voltage controlled oscillator 5p. 
By repeating a series of these operations, finally the phase of the external reference clock line CLex 11p and the phase of the internal clock line CLin 12p are synchronized with each other, and at the output of the voltage controlled oscillator 5p a signal (a clock) synchronized with the external reference clock line CLex 11p, the frequency of the signal being N-times multiplied (N is a frequency dividing ratio of the frequency divider 6p), is obtained.
However, in the multiplication clock generator by the conventional dual loop PLL, the frequency comparison and phase comparison are carried out by the same reference clock, and the frequency comparison operation and phase comparison operation are carried out during the initial start-up of the dual loop PLL, thereby increasing the lock-up time. Moreover, the increase of the lock-up time would be a cause of the increased power dissipation. In digital systems such as a portable communication apparatus, although as a method for reducing the power dissipation of systems there is a technique of intermittently operating the clock, the reduction of the lock-up time will be a problem in case of intermittently operating the dual loop PLL.